One-time programmable memory is one type of non-volatile memory. FIG. 1A shows a cross-sectional view of an anti-fuse one-time programmable memory cell 10. In FIG. 1A, the anti-fuse one-time programmable memory cell 10 comprises a P well region 101, a gate structure 102, a gate structure 103, a first N-type doped region 104, a second N-type doped region 105, a third N-type doped region 106 and N-type lightly doped drains (NLDD) 107-110, wherein the gate structure 102, the first N-type doped region 104, the second N-type doped region 105 and the N-type lightly doped drains 107-108 constitute a selection transistor 11, and the gate structure 103, the second N-type doped region 105, the third N-type doped region 106 and N-type lightly doped drains 109-110 constitute a programmable transistor 12. The first N-type doped region 104 of the selection transistor 11 is electrically connected to a bit line BL, and the gate structure 102 of the selection transistor is electrically connected to a word line WL.
FIG. 1B illustrates that permanent conductive paths 18 and 19 could be formed in the programmable transistor 12 of the anti-fuse one-time programmable memory cell 10 during the programming operation. In FIG. 1B, during a programming operation, the voltage of the bit line BL is 0, a voltage which is higher than a threshold voltage of the selection transistor is provided to the word line WL, and a high voltage (programming voltage) is provided to the gate structure 103 of the programmable transistor 12. At this time, the selection transistor 11 is on, and the programming voltage provided to the gate structure 103 induces a voltage between the gate structure 103 and the second N-type doped region 105 of the programmable transistor 12. The induced voltage results in breakdown occurring in the gate oxide layer (or gate dielectric layer) of the gate structure 103 of the programmable transistor 12 causing the gate oxide layer to rupture. When the rupturing of the gate oxide layer occurs between the gate structure 103 and the P well region 101, a permanent conductive path 18 is formed between the P well region 101 and the gate structure 103. When the rupturing of the gate oxide layer occurs between the gate structure 103 and the N-type lightly doped drain 109, a permanent conductive path 19 is formed between the second N-type doped region 105 and the gate structure 103.
FIGS. 1C-1E show equivalent circuit diagrams of the anti-fuse one-time programmable memory cell 10 before and after programming. In FIG. 1C, the anti-fuse one-time programmable memory cell 10 has not performed a programming operation. At this time, the anti-fuse one-time programmable memory cell 1 includes a selection transistor 11 and a programmable transistor 12. In FIG. 1D, the anti-fuse one-time programmable memory cell 10 accomplishes the programming operation and the permanent conductive path 18 is formed correspondingly. At this time, the programmable transistor 12 is equivalent to a resistor R1 constituted by the permanent conductive path 18. In FIG. 1E, the anti-fuse one-time programmable memory cell 10 accomplishes the programming operation and the permanent conductive path 19 is formed accordingly. At this time, the programmable transistor 12 is equivalent to a resistor R2 constituted by the permanent conductive path 19.
Back to FIG. 1B, the permanent conductive paths 18 and 19 have different resistances. For the anti-fuse one-time programmable memory cell 10, an equivalent resistance of the permanent conductive path 18 is lower than the equivalent resistance of the permanent conductive path 19 in a read operation so that conduction current flowing through the permanent conductive path 18 is greater than conduction current flowing through the permanent conductive path 19 with an identical read voltage. Accordingly, if a permanent conductive path 18 is formed in the programming operation, a sense amplifier from outside the anti-fuse one-time programmable memory cell 10 can read larger conduction currents. On the other hand, if only the permanent conductive path 19 is formed in the programming operation, then lower conduction current flowing through the permanent conductive path 19 could result in misjudgment by the sense amplifier. In addition, rupture positions of the gate oxide layer (or gate dielectric layer) are randomly distributed and cannot be controlled by the programming voltage provided to the gate structure 103 of the programmable transistor 12.
Accordingly, how to let a breakdown occurring on the N-type lightly doped drain 109 form the permanent conductive path 18 (or to avoid only forming the permanent conductive path 19) becomes an important issue.